Field of the Invention
The present invention relates to a delay circuit, and more particularly to an all-digital delay circuit.
Description of the Related Art
With the advancement of semiconductor technology, the operating frequency of integrated circuits has become faster, and a situation of unsynchronization between the internal and external components of integrated circuits has become worse. To eliminate the unsynchronization situation, a phase locked loop (PLL) circuit or a delay-locked loop (DLL) circuit is applied to calibrate clock signals to ensure the clock phases of each components of the integrated circuits are the same. Generally, the PLL circuit comprises a voltage-controlled oscillator, and jitter in a PLL circuit causes the noise immunity of the PLL circuit to be worse than the noise immunity of a DLL circuit.
DLL circuits can be classified into two categories: analog DLL circuits and digital DLL circuits. In a digital DLL circuit, a digital delay line is applied to cause phase delay. However, a conventional digital delay line needs at least two components to cause phase delay, and the basic delay time of a digital delay line is too large under high-speed transmission. The phase calibration may be correctly executed accordingly.
FIG. 1A is a schematic diagram of a conventional digital delay line. The digital delay line shown in FIG. 1A uses 3 NAND gates, wherein the delay time of each NAND gate is Td. Thus, the minimum delay time of the delay line in FIG. 1A is 2Td. The delay line of FIG. 1A has two delay paths. A first delay path is formed by the NAND gates 11 and 13, and a second delay path is formed by NAND gates 12 and 13. When a clock signal CLKA passes the first delay path, a phase delay of 2Td is generated on the clock signal CLKA. Similarly, when a clock signal CLKB passes the second delay path, a phase delay of 2Td is generated on the clock signal CLKB. However, if the phase delay required by the clock signal CLKA or CLKB is less than 2Td, the digital delay line of FIG. 1A is not appropriate to provide the phase delay.
FIG. 1B is a schematic diagram of another conventional digital delay line. In FIG. 1B, the delay time of NAND gate 101 or 102 is Td, and the delay time of the inverter 103 is T. If the phase delay required by the clock signal CLKA or CLKB is less than 2Td or (Td+T), the digital delay line of FIG. 1B is not appropriate to provide the phase delay.